1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to techniques for improving contact structures providing electrical and thermal chip-package connections.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate semiconductor material. The majority of semiconductor devices including highly complex electronic circuits are currently and, in the foreseeable future, will be manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as SOI (silicon-on-insulator) substrates, viable base materials for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs), systems on chip (SoC) and the like. The individual integrated circuits are arranged in an array on the wafer, wherein most of the manufacturing steps, which may involve several hundred and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economical constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing the number of devices per substrate.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In the attempt to maximize the useable surface area for a given substrate size, the feature sizes of circuit elements are steadily scaled down. Due to this ongoing demand for shrinking the feature sizes of the circuit elements of highly sophisticated semiconductor devices and consequently also of the structures connecting the circuit elements, copper in combination with a low-k dielectric material has become a frequently used alternative in the formation of the so-called interconnect structures comprising metal line layers and inter-mediate via layers that include metal lines as intra-layer connections and vias as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other is necessary to realize the connections between all internal circuit elements and to provide the required I/O (input/output), power and ground contact pads of the circuit design under consideration. The stacked metal line layers and via layers form a metallization system, wherein the contact pads may be formed in or on the upper or last metallization layer and may comprise any appropriate metal or alloy comprising, e.g., aluminum, copper, platinum, gold or silver. A passivation system comprising silicon nitride, silicon oxide, silicon carbide and/or organic passivation layers such as, e.g., polyimide, may be formed above the metallization system and on the contact pads. An opening is formed in the passivation system by well-established lithography and etching techniques so that the contact pads are at least partially exposed to allow for electrically and thermally connecting the device, e.g., with a package substrate. The exposed contact pad material, however, may be adversely affected, e.g., by the ambient atmosphere during and between dicing and packaging processes, in particular when sensitive materials such as copper and aluminum are employed.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements, such as field effect transistors and the like, but is limited, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased in combination with a reduced conductivity of the lines due to a reduced cross-sectional area. For this reason, traditional dielectrics such as silicon dioxide (k>4) and silicon nitride (k>7) are replaced by dielectric materials having a lower permittivity, which are, therefore, also referred to as low-k dielectrics having a relative permittivity of 3 or less. However, the density and mechanical stability or strength of the low-k materials may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride. As a consequence, during the formation of the metallization system and any subsequent manufacturing processes of integrated circuits, production yield may depend on the mechanical characteristics of sensitive dielectric materials, such as low-k and ultra low-k (ULK) dielectric layers, and their adhesion to other materials.
In addition to the problems of reduced mechanical stability of advanced dielectric materials having a dielectric constant of 3.0 and significantly less, device reliability may be affected by these materials during operation of sophisticated semiconductor devices due to an interaction between the chip and the package caused by a thermal mismatch of the corresponding thermal expansion of the different materials. For instance, in the fabrication of complex integrated circuits, increasingly a contact technology may be used in connecting the package carrier to the chip, which is known as flip chip packaging technique. Contrary to the well-established wire bonding techniques in which appropriate contact pads may be positioned at the periphery of the very last metal layer of the chip, which may be connected to corresponding terminals of the package by a wire, in the flip chip technology, a respective bump structure may be formed on the last metallization layer, for instance comprised of a solder material, which may be brought into contact with respective contact pads of the package. Thus, after reflowing the bump material, a reliable electrical and mechanical connection may be established between the last metallization layer and the contact pads of the package carrier. In this manner, a very large number of electrical connections may be provided across the entire chip area of the last metallization layer with reduced contact resistance and parasitic capacitance, thereby providing the IO (input/output) capabilities, which may be required for complex integrated circuits, such as CPUs, storage memories and the like.
During the corresponding process sequence for connecting the bump structure with a package carrier, a certain degree of pressure and/or heat may be applied to the composite device so as to establish a reliable connection between each of the bumps formed on the chip and the bumps or pads that may be provided on the package substrate. The thermally or mechanically induced stress may, however, also act on the lower-lying metallization layers, which may typically include low-k dielectrics or even ultra low-k dielectric materials, thereby significantly increasing the probability of creating defects by delamination of these sensitive materials due to reduced mechanical stability and adhesion to other materials.
Moreover, during operation of the finished semiconductor device attached to a corresponding package substrate, also significant mechanical stress may occur due to a significant mismatch in the thermal expansion behavior of the silicon-based semiconductor chip and the package substrate, since, in volume production of sophisticated integrated circuits, economic constraints typically require the usage of specified substrate materials for the package, such as organic materials, which typically may exhibit a different thermal conductivity and a coefficient of thermal expansion compared to the silicon chip.
The thermal and electrical performance of a “bump structure” may be further increased by providing metal pillars instead of solder bumps or balls, thereby reducing the required floor space for individual contact elements. Furthermore, the thermal and electrical conductivity may be enhanced due to the superior characteristics of the employed metals compared to typically used solder material, in particular when metals exhibiting a high conductivity, such as, e.g., copper, silver or copper alloys, are used for forming the pillars. A semiconductor device comprising metal pillars may be described in more detail with reference to FIG. 1a. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a conventional metal pillar configuration. The semiconductor device 100 may typically comprise a substrate 101, for instance a silicon substrate or an SOI substrate, depending on the overall configuration of the circuit layout and the performance of the manufactured integrated circuit. Moreover, a silicon-based semiconductor layer 102 may typically be provided above the substrate 101, wherein the semiconductor layer 102 may comprise a very large number of circuit elements, such as transistors 155, capacitors (not shown), resistors (not shown) and the like, as are required for the desired functional behavior of the integrated circuit. As previously discussed, the ongoing shrinkage of critical dimensions of circuit elements may result in critical dimensions of transistors on the order of magnitude of 40 nm and significantly less in presently available sophisticated semiconductor devices produced by volume production techniques. The semiconductor device 100 comprises a metallization system 110, which, in advanced devices, comprises a plurality of metallization layers 120, 130, 140, i.e., of device levels, in which metal lines 135 and vias 134 and possibly contact metal regions 145 are embedded in an appropriate dielectric material. As discussed above, at least a portion of the corresponding dielectric materials used in the various metallization layers is usually comprised of materials of reduced mechanical stability in order to reduce the parasitic capacitance of adjacent metal lines 135. As previously explained, the pillar structure 166 may be provided above the metallization system 110, wherein the corresponding metal pillars 166 are provided on a contact pad 181 formed on the very last metallization layer 140 of the metallization system 110. The contact pad 181 may be encapsulated by a passivation layer 161. A metal layer system 165 comprising two or more sub-layers is arranged between the metal pillar 166 and the contact pad 181. The metal layer system 165 may comprise metals, such as, e.g., titanium, copper, chromium, tungsten or gold or combinations thereof, that are appropriate to provide a reliable interface with regard to adhesion of the pillar and pad materials. Furthermore, the upper layer of the metal layer system 165 may serve as a seed layer. The metal layer system 165 may further provide the required current distribution functionality in case the metal pillar is formed by electrochemical plating techniques. The pillars may be formed by means of a resist mask (not shown) defining the size and position of the pillars. The corresponding resist mask may be formed by well-established lithography techniques.
After resist removal, also the exposed portions of the metal layer system 165 are removed by an appropriate etch chemistry using dry or wet etch processes, thereby exposing the passivation layer 161 and a portion of the contact pad 181. Subsequently, a further passivation layer 162 providing, in combination with passivation layer 161, a passivation layer system 160 formed on the device 100.
The processing up to this manufacturing stage may be performed on the basis of the substrate 101 comprising a plurality of die or chip regions. Frequently, the further processing may be continued in a remote manufacturing facility in which dedicated process equipment and manufacturing strategies are implemented so as to finalize the device, which typically includes dicing the substrate into individual semiconductor chips and device packaging. Consequently, the substrate 101 may be transported to a different manufacturing environment which, however, may result in a certain degree of surface contamination, for instance by corrosion and the like.
The metal pillars may further contribute to an even more severe interaction between the package and the metallization system of the chip, since typically the metal pillars are significantly less deformable compared to the bump structures, which may be advantageous in view of electrical and thermal behavior, which, however, may result in even increased mechanical stress components in a locally very restricted manner when the chip is connected to a package substrate, as will be described in more detail with reference to FIG. 1b. 
FIG. 1b schematically illustrates a cross-sectional view of an integrated circuit 150 comprising a semiconductor die or chip 100 connected to a package substrate 170 that is substantially comprised of an organic material, such as appropriate polymer materials and the like, wherein the connection between the chip 100 and the package substrate 170 may be accomplished by means of a pillar structure 166. The package substrate 170 comprises appropriately positioned and dimensioned contact pads 190 which may be brought into contact with corresponding pillars or any solder material formed thereon, in order to establish respective mechanical and electrical connections upon application of heat and/or mechanical pressure. Furthermore, the package substrate 170 usually comprises appropriate conductive lines in order to connect the upper portion of the pillar structure 166 with corresponding terminals, which then establish an electrical interface to other peripheral components, such as a printed wiring board and the like. For convenience, any such conductive lines are not shown. A gap formed between the chip 100 and the package substrate 170 is filled by an appropriate underfill material 175, wherein the underfill material 175 may come in contact with exposed portions of the contact pads 181.
During operation of the integrated circuit 150, heat is generated within the semiconductor chip 100, for instance caused by the circuit elements, e.g., transistor 155 (FIG. 1a) formed in and above the semiconductor layer 102. This waste heat is dissipated, for instance, by the metallization system 110 and the pillar structure 166 in a highly efficient manner and/or via the substrate 101, depending on the overall thermal conductivity of the substrate 101. For example, the heat dissipation capability of SOI substrates is significantly less compared to pure silicon substrates due to the reduced thermal conductivity of the buried insulating oxide layer, which separates the semiconductor layer 102 from the remaining substrate material. Thus, a major heat dissipation path is provided by the pillar structure 166 and the package substrate 170. Consequently, a moderately high average temperature is created in the semiconductor chip 100 and also in the package substrate 170, wherein, as previously discussed, a mismatch in the coefficient of thermal expansion between these two components may cause a significant mechanical stress. The package substrate 170 may have an increased thermal expansion compared to the semiconductor chip 100, wherein a corresponding mismatch, therefore, results in a significant degree of thermal stress, in particular at the “interface” between the semiconductor chip 100 and the package substrate 170, that is, in particular, the pillar structure 166 and the metallization system 110 may experience significant sheer forces caused by the thermal mismatch during the operation of the integrated circuit 150. Due to the reduced mechanical stability and the reduced adhesion of sophisticated dielectric materials, corresponding defects may occur, which may affect the overall reliability of the integrated circuit 150. In particular, the stiffness of the individual pillars of the pillar structure 166 may result in locally high sheer forces, which are transferred into the entire metallization system, thereby resulting in delamination defects and the like.
The height of the metal pillars may be adjusted so that the spacing between the package substrate and the chip is appropriate for a reliable filling in of an underfill material 175 that may reduce sheer forces transferred into the metallization system. Voids in the underfill material or insufficient adhesion of the underfill material 175 to the exposed portions of contact pads 181, however, may also contribute to a high degree of non-reliability, for instance caused by non-uniformities in heat conductivity and the like.
Consequently, although advanced contact regimes between a chip and a package substrate based on metal pillars may provide significant advances with respect to heat dissipation capabilities and electrical conductivity for a reduced required floor space, thereby allowing enhanced density of contact elements and/or dummy elements for heat dissipation, the increased mechanical stress induced in the metallization system and/or insufficient adhesion of the underfill material to exposed portions of contact pads 181 may not be compatible with the reliability requirements of the semiconductor devices.
In view of the situation described above, the present disclosure relates to methods and semiconductor devices in which a pillar structure may be provided, while avoiding or at least reducing one or more of the problems identified above.